1. Field of the Invention
The present invention relates to three-dimensional (3D) graphics processing, and more particularly, to a 3D graphics accelerator, a pixel cache for the 3D graphics accelerator, and a method of accelerating 3D graphics.
2. Description of the Related Art
Three-dimensional (3D) graphics is a technique of depicting an object in a 3D space using three axes such as the height, width, and length of the object and then more realistically displaying the object on a two-dimensional (2D) monitor screen. A 3-D graphics accelerator is an apparatus that speeds up 3-D graphics and which works by receiving a geometric figure depicted using a shaping modeler, changing some parameters such as a camera angle or a light source of the geometric figure, and outputting an image (or arrangement of pixels) of the geometric figure corresponding to the changed parameters.
A series of processes performed by the 3D graphics accelerator is called a graphics pipeline. Even if a delay in only one of the processes included in the graphics pipeline is caused, the full speed of the pipeline decreases. The graphics pipeline includes a geometry processing and a rendering processing. The amount of computation in the geometry processing is proportional to the number of apexes of a polygon to be processed, whereas the amount of computation in the rendering processing is proportional to the number of pixels.
During a graphics processing on a high-definition monitor, an increase in the number of pixels requires an increase in the operating speed of a rendering engine that performs a rendering processing. To increase the rendering speed, there is a need of improving the internal structure of the rendering engine, or increasing the number of rendering engines and arranging the rendering engines in parallel.
However, it is most effective to reduce a frequency to access a memory, i.e., to reduce a memory bandwidth, in order to increase the processing speed of the rendering engine. To display an image on a 2D monitor screen, texture data and pixel data, which are stored in the memory, need to be processed. To reduce the frequency to access the memory, installation of a cache into a graphics accelerator is indispensable.
In general, a 3D-graphics rendering processor uses a pixel cache that stores depth-data, i.e., z-data, and color data. The hit ratio of the pixel cache is remarkably lower than that of a microprocessor cache. A high hit ratio of cache increases the probability of reusing data stored in the cache, thus reducing the frequency to access the memory. Accordingly, an effective structure of the pixel cache is required to increase the probability of the hit ratio of the pixel cache.
The performance of 3D-graphics hardware is strongly affected by the memory speed. Although the memory is dependent on factors such as data structure, memory structure, and frequency of accessing the memory, there is not much research on these topics. A recent paper by Mitra and Chiuh provides an analysis of a dynamic workload, in which the analysis is related only to use of texture traffics and memory banks during a rasterization process. In addition, techniques to solve problems caused by texture data dealt only with a texture cache or a texture first-in, first-out (FIFO) procedure. Moreover, research on a pixel cache is in an initial phase.